Skew processor clocks (TSC register) on SMP systems

SKEW: Skew processor clocks (TSC register) on SMP systems

Syntax:
  skew [-s [#sec]] [-q]

Where:
  -s   Skew the clocks.
       * If #sec is specified then clocks are skewed #secs from
         each other.
       * If #sec is not specified then clocks are skewed 60 secs
         (1 min) from each other.
       * The highest numbered processor will have the largest skew
         (relative to processor 0). Processor 0 will have the smallest
         skew.
       * Clock skew is displayed at completion of the command.
  -q   Query clock skew.
       * Displays current value of TSC for all processors
         and the difference from processor 0's TSC and from the TSC
         from the next mumerically lower processor number.

Notes:
  * Skewing is accomplished by resetting (to 0) the TSC register.
    Any code that relies on the TSC not going backwards may have
    problems.
  * The command won't complete until all clocks are skewed. So, for
    example, if you request clocks to be skewed by 2 minutes on an
    8-way SMP machine, the command will run for 14 minutes.
  * Skew display data fields:
    - TSC:
         Current value of the TSC
    - Delta (CPU0):
         Difference in values between this processor and processor 0.
         The difference is expressed as an absolute value.
    - Delta (prev CPU):
         Difference in values between this processor and previous
         (numerically lower) processor. The difference is expressed
         as an absolute value.
    - Time:
         Approximate time, in seconds, represented by the cycles value.
         May display as 0 (zero) for very small skews.

Examples:
  1) The following both skew the clocks by 60 seconds:
     * skew -s
     * skew -s 60
  2) Display current clock skew:
     - skew -q
  3) Sample output on system where clocks are not skewed:
                                        Delta (CPU0)          Delta (prev CPU)
                TSC Value             Cycles      Time        Cycles      Time
           -------------------   ---------------  ----   ---------------  ----
     CPU0: 0x00000007:8BF43FD8   0x0000:00000000   0.0   0x0000:00000000   0.0
     CPU1: 0x00000007:8BF53540   0x0000:0000F568   0.0   0x0000:0000F568   0.0
     CPU2: 0x00000007:8BF45118   0x0000:00001140   0.0   0x0000:0000E428   0.0
     CPU3: 0x00000007:8BF554F8   0x0000:00011520   0.0   0x0000:000103E0   0.0

  4) Sample output on system where clocks are skewed:
                                        Delta (CPU0)          Delta (prev CPU)
                TSC Value             Cycles      Time        Cycles      Time
           -------------------   ---------------  ----   ---------------  ----
     CPU0: 0x00000000:000198E8   0x0000:00000000   0.0   0x0000:00000000   0.0
     CPU1: 0x0000000D:F0650204   0x000D:F063691C  25.0   0x000D:F063691C  25.0
     CPU2: 0x0000001B:E0C43A30   0x001B:E0C2A148  50.0   0x000D:F05F382C  25.0
     CPU3: 0x00000029:D09D62AC   0x0029:D09BC9C4  75.0   0x000D:EFD9287C  25.0