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Read/Write Machine Specific Registers
MSR: Read and Write P4/P6/Core/Core2/AMD64 MSRs
Syntax:
msr -r [msr_num | msr_name] <-c cpu_num> (READ)
msr -w [msr_num | msr_name] value <-c cpu_num> (WRITE)
msr -n msr_num (NAME-FROM-MSR)
msr -m msr_name (MSR-FROM-NAME)
msr -l (LIST-NAMES)
Where:
-r Read MSR.
-w Write 'value' to MSR.
-c Specifies processor(s) to read from or write to.
- Valid values are: 'all' or a processor number.
- Default is 'all' processors.
-n Get MSR name from MSR number.
-m Get MSR number from MSR name.
-l List valid MSR names.
msr_num is any valid msr number, in decimal or hexadecimal.
msr_name is any of the names returned by "msr -l".
These are some commonly used msr names:
MSR Corresponding MSR number
name P6/Core P4/Netburst AMD64
---- ------- ----------- ----------
ctr0 0xC1 0x300 0xC0010004
ctr1 0xC2 0x301 0xC0010005
ctr2 -- 0x302 0xC0010006
ctr3 -- 0x303 0xC0010007
...
ctr17 0x311 --
fixed_ctr0 0x309 -- --
fixed_ctr1 0x30A -- --
fixed_ctr2 0x30B -- --
evtsel0 0x186 -- 0xC0010000
evtsel1 0x187 -- 0xC0010001
evtsel2 -- -- 0xC0010002
evtsel3 -- -- 0xC0010003
cccr0 -- 0x360 --
...
cccr17 -- 0x371 --
fixed_ctr_ctrl 0x38D -- --
global_ctrl 0x38F -- --
global_ovf_ctrl 0x390 -- --
global_status 0x38E -- --
tsc 0x10 0x10 0x10
perf_status -- 0x198 --
perf_ctl -- 0x199 --
efer(*) 0xC0000080 0xC0000080 0xC0000080
star(*) 0xC0000081 0xC0000081 0xC0000081
lstar(*) 0xC0000082 0xC0000082 0xC0000082
cstar(*) 0xC0000083 0xC0000083 0xC0000083
sfmask(*) 0xC0000084 0xC0000084 0xC0000084
fsbase(*) 0xC0000100 0xC0000100 0xC0000100
gsbase(*) 0xC0000101 0xC0000101 0xC0000101
kgsbase(*) 0xC0000102 0xC0000102 0xC0000102
(*) These registers exist in Intel64-capable Intel
processors and in all AMD64 AMD processors.
Notes:
* Hexadecimal numbers must be prefixed with '0x'.
* 'value' is a decimal or hexadecimal number.
- If larger than 64-bits it will be truncated to 64-bits.
- If smaller than 64-bits it will be zero-extended to 64-bits.
* MSR names are *NOT* case sensitive.
- 'TSC', 'tsc', 'TsC' and 'tSc' all mean the same.
* For MSRs that have more than one name, either name can be used.
- On any Intel/AMD x86/x64 machine:
- 'TIME_STAMP_COUNTER' and 'TSC' both refer to MSR 0x10.
- On an Intel Core/Core2 machine:
- 'PMC0' and 'CTR0' both refer to MSR 0xC1.
- On an Intel P4/Netburst machine:
- 'BPU_COUNTER0' and 'CTR0' both refer to MSR 0x300.
- On an AMD machine:
- 'PerfCtr0' and 'CTR0' both refer to MSR 0xC0010004.
* Neither 'msr_num' nor 'value' are checked for validity.
- Be *VERY* careful with the values you write and to which
MSR you write it to. You have the ability to cause major
problems. Consider yourself warned!
- If 'msr_num' is invalid then nothing is read nor written.
- I would stay away from writing to the EFER, LSTAR and similar
MSRs used by the OS. You are asking for *BIG* trouble if you
modify any of those registers.
* For performance counters only the low order 40 (Intel) or 48 (AMD)
bits are written and/or read.
* All other values displayed (on reads) are the raw 64-bit values.
Some MSRs are only 32-bits and others are 64-bits. You decide how
to interpret the values.
Examples:
1) Read TSC on all processors:
- msr -r 16
- msr -r 0x10
- msr -r tsc
- msr -r 16 -c all
- msr -r 0x10 -c all
- msr -r tsc -c all
2) Read TSC on processor 1:
- msr -r 0x10 -c 1
3) Reset TSC on all processors:
- msr -w 0x10 0
- msr -w tsc 0
4) Read P6 ctr0 on all processors:
- msr -r 0xc1
- msr -r 0x193
- msr -r ctr0
5) Set P6 EvtSel0 (ctr0) to count INSTR_RETIRED:
- msr -w 0x186 0x004300c0
- msr -w evtsel0 0x004300c0
6) Read P4 ctr12 on all processors:
- msr -r 0x30c
- msr -r 780
- msr -r ctr12
7) Read Opteron/Athlon64 ctr3 on all processors:
- msr -r 0xc0010007
- msr -r 201330695
- msr -r ctr3
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